1. Field of the Invention
The present invention relates to an isochronous serial time division multiplexer and, in particular, to an isochronous serial time division multiplexer that routes isochronous data without buffering the data in a random-access memory.
2. Description of the Related Art
An isochronous time division switch is a device that routes the isochronous data output from a plurality of isochronous data sources to a plurality of isochronous data sinks. In general terms, isochronous data sources and sinks are devices, such as video cameras and telephones, that continuously transmit or receive data at a constant data rate.
When the data rate required by a particular isochronous data source is relatively small, the data from several isochronous data sources can be interleaved together so that the data from each of the sources can be effectively transferred at the same time.
Conventionally, an eight kilohertz framing signal is utilized to form a continuous series of 125 .mu.S frames which, in turn, are divided into a series of time slots. Each time slot then defines the boundaries for a portion of the data which is output from an isochronous data source. Thus, for example, the first, fourth, and seventh time slots of each frame could contain data from one isochronous data source, while :he second, fifth, and eighth time slots contain data from another isochronous data source.
An isochronous time division switch, in turn, routes the data in each of the time slots from several input streams of data to several output streams of data. FIG. 1 shows a block diagram that illustrates a conventional isochronous time division switch 10.
As shown in FIG. 1, switch 10 receives three input streams of isochronous data I1-I3, and forms three output streams of isochronous data O1-O3. For purposes of illustration, only one frame of data is shown for each stream of data I1-I3 and O1-O3, and each frame of data is divided into 10 time slots.
In operation, switch 10 receives and stores the data contained in each of the time slots that form one frame of data from each of the input streams of data I1-I3 in one of the two pages of random-access-memory (RAM). Thus, for example, the data contained within all 30 time slots (3 data streams each having 10 time slots each in one frame of data) could be stored in RAM page 0.
Once completed, RAM page 0 and RAM page 1 are switched on the 125 .mu.S frame boundary so that the data contained in each of the time slots that form the next frame of data from each of the input streams of data I1-I3 are stored in RAM page 1. At the same time, the data stored in RAM page 0 is output into the time slots of the three output streams of data O1-O3.
The advantage of this type of scheme where the two pages of RAM take turns receiving and transmitting data is that the mapping relationship between the incoming and outgoing time slots is completely arbitrary. As a result, the data which is contained within one of the input time slots can be output in any of the time slots of any of the output data streams O1-O3. Thus, for example, the data within the second time slot of input stream I2 could be output in the first time slot of output stream O1, the fifth time slot of output stream O2, and/or the third time slot of output stream O3.
One problem with this dual-RAM type of multiplexing, however, is that a significant amount of RAM is required to hold the data from all of the time slots from one frame of data. Since RAM is costly, there is a need for a time division switch that can operate without the RAM.